Booster circuit

ABSTRACT

The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

This application is a 371 of PCT/JP03/12336 filed on Sep. 26, 2003.

TECHNICAL FILED OF THE INVENTION

The present invention relates to a semiconductor charge pump circuit forgenerating a voltage higher than an operating voltage or generating anegative voltage, and to a semiconductor integrated circuit using thesame.

BACKGROUND OF THE INVENTION

When a non-volatile memory such as a Flash or EEPROM is deleted orwritten, a tunnel effect, hot electron, or hot hole is used, so that ahigh voltage of approximately 12 V is required. As a conventionalcharge-pump type booster circuit which generates a high voltage, aDicson charge pump diode-connected to a MOS transistor (hereinafter,“transfer MOS”) moving electric charges has been generally known andoften used because a circuit configuration thereof is very simple. Sucha Dicson charge pump is presented and analyzed in “A Dynamic Analysis ofthe Dicson Charge Pump”, IEEE, JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32,No. 8, Aug. 1997. FIGS. 1 and 2 show structural diagrams of the Dicsoncharge pump. FIG. 1 is a conceptual block diagram disclosed also in theabove IEEE document, and FIG. 2 is an example in which buffers in FIG. 1are replaced by n-type MOSS. In FIG. 2, a drain and gate of the n-typeMOS are short-circuited, and a CLK is applied to one side of acapacitance connected to the drain and source. The CLK and a CLKn have acomplementary relation, as shown in FIG. 3. When the CLKn is “High” andthe CLK is “Low”, drain potentials at odd-th stages such as first andthird stages are higher than a source potential. Therefore, a draincurrent flows through the n-type MOSs at the odd-numbered stages,whereby electric charges are charged in odd-th capacitances C1 and C3.Conversely, when the CLK is “High” and the CLKn is “Low”, the drainpotentials at even-th stages such as second and fourth stages are higherthan the source potential. Therefore, a drain current flows through then-type MOSs at the even-th stages, whereby electric charges are chargedmove from the odd-th capacitances C1 and C3 to even-th capacitances C2and C4.

If it is assumed that each threshold voltage of n-type MOS transistorsconfiguring the Dicson charge pump is Vt, an output voltage Vout thereofcan be represented by:Vout=(Vcc−Vt)×N+Vcc  (1)

-   -   N: number of stages and Vcc: power-supply voltage.        However, as approaching an output side, the drain and source        voltages of the n-MOS transistor are boosted and, by an        substrate effect caused due to an increase in a source-substrate        voltage Vsb, a threshold voltage Vt of an NMOS transistor is        increased as shown in the following Equation (2):        Vt=Vt0+γ(√{square root over (2φf+Vsb)}−√{square root over        (2φf)})  (2)    -   Vt0: Vt at Vsb=0 V, γ: substrate effect coefficient, and φf:        Fermi level of substrate.        Furthermore, since the Vsb at Vt=Vcc means the maximum voltage        of boosted voltages obtained from the equation (2),

$\begin{matrix}{{{Vout\_ max}\left( {= {Vsb}} \right)} = {\left( {\frac{{Vcc} - {Vt0}}{\gamma} + \sqrt{2\phi\; f}} \right)^{2} - {2\phi\; f}}} & (3)\end{matrix}$and therefore the maximum boosted voltage Vout_max can be calculatedfrom the formula (3). FIG. 4 shows calculation values of thepower-supply voltage Vcc and the boosted voltage Vout. As seen from FIG.4, it is understood that in the Dicson charge pump, the boosted voltageVout_max is determined depending on the power-supply voltage Vcc.

An improved version of Dicson charge pump has also been studied. In a“charge pump circuit device” disclosed in Japanese Patent Laid-Open No.11-308856, the n-type MOSs are separated into a plurality of groups tosuppress an increase in the Vt of the n-type MOS due to the substrateeffect caused by increasing gradually the substrate voltage.

As the above-described Dicson charge pump that is a conventionaltechnique is boosted, the source-substrate voltage Vsb of the n-type MOSis increased and thereby the threshold voltage Vt of the n-type MOS isincreased due to an influence of the substrate effect, so that themaximum value of the boosted voltage is determined. As a result, by alow power-supply voltage equal to or lower than 3 V, a high voltage ofapproximately 12 V required for deleting or writing the non-volatilememory cannot be generated.

Moreover, even when the “charge pump circuit device”, which is disclosedin Japanese Patent Laid-Open No. 11-308856 and in which the n-type MOSsare separated into the plurality of groups to suppress an influence ofthe substrate effect caused by increasing gradually the substratevoltage, is used, there are the n-type MOSs not meeting Vsb=0 V, so thatit is impossible to eliminate the substrate effects of all the n-typeMOSs.

Also, “Semiconductor charge pump circuit and non-volatile semiconductorstorage device” in Japanese Patent Laid-Open No. 2003-45193 discloses ascheme in which a charge voltage at a stage that precedes theimmediately preceding stage is a substrate potential of the n-type MOS,wherein the different voltage values for each stage are set as thesubstrate potentials of the n-type MOS. However, the Vsb becomes avoltage-amplified value Vga (=Vcc−Vt) for at least one stage, so thatthe substrate effect is caused.

An object of the present invention is to provide a charge pump circuithaving no influence of the substrate effects, and also to provide thecharge pump circuit having an efficient circuit configuration andcapable of generating a plus or minus high voltage.

DISCLOSURE OF THE INVENTION

In order to solve the above problems, a MOS which controls the substrateof the n-type MOS transferring electric charges is added. If there isthe n-type MOS, the substrate potential is always set to a drain orsource potential, whichever is lower in potential, to meet Vsb=0 V,whereby the influence of the substrate effect is eliminated.

When Vsb=0 V, the second term of the Equation (2) can be made 0, but theVt0 in the first term is left. In order that this Vt0 of the n-type MOSis made 0 V, a voltage equal to or higher than (power-supplyvoltage+Vt0) is applied to a gate of the n-type MOS via a capacitance Cgand, at the same time, the gate voltage set in the n-type MOS is used tocontrol a gate potential of an n-type MOS at the next stage, wherebycharge-transfer efficiency is enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural diagram of a conventional Dicson charge pump.

FIG. 2 is a circuit diagram of the conventional Dicson charge pump.

FIG. 3 is a chart showing clock waveforms.

FIG. 4 is a graph indicative of boosted-voltage calculation values ofthe Dicson charge pump.

FIG. 5 is an entire circuit diagram of a charge pump circuit accordingto a first embodiment of the present invention.

FIG. 6 is a partial circuit diagram of the charge pump circuit accordingto the first embodiment of the present invention.

FIG. 7 is a circuit's explanatory diagram of the charge pump circuitaccording to the first embodiment of the present invention in a periodof CLK X1.

FIG. 8 is a circuit's explanatory diagram of the charge pump circuitaccording to the first embodiment of the present invention in a periodof CLK X2.

FIG. 9 is a timing chart of the charge pump circuit according to thefirst embodiment of the present invention.

FIG. 10 is a simulated circuit diagram of the charge pump circuitaccording to the first embodiment of the present invention.

FIG. 11 is a graph representing simulation results of the charge pumpcircuit according to the present invention.

FIG. 12 is a twice boosted CLK circuit.

FIG. 13 is a diagram of a minus-high-voltage generating charge pumpcircuit according to a second embodiment of the present invention.

FIG. 14 is a circuit's explanatory diagram of the charge pump circuitaccording to the second embodiment of the present invention in theperiod of CLK X1.

FIG. 15 is a circuit's explanatory diagram of the charge pump circuitaccording to the second embodiment of the present invention in theperiod of CLK X2.

FIG. 16 is a diagram of a plus-high-voltage generating charge pumpcircuit showing a third embodiment of the present invention.

FIG. 17 is a diagram of a minus-high-voltage generating charge pumpcircuit showing a fourth embodiment of the present invention.

FIG. 18 is a diagram of a plus-and-minus high-voltage generating chargepump circuit showing a fifth embodiment of the present invention.

FIG. 19 is a diagram of a high-voltage generating charge pump circuitshowing a sixth embodiment of the present invention.

FIG. 20 is a serial-type charge pump circuit showing a seventhembodiment of the present invention.

FIG. 21 is a hardware structure of an IC card on which the charge pumpcircuit according to the present invention is mounted.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be describedaccording to the drawings. Although not being limited, circuit elementsin the present invention are realized by a well-known Si semiconductorintegrated circuit. In the drawings of the present application, acomponent whose back gate has an arrow directed inwardly represents ann-type MOSFET. Also, a component whose back gate has an arrow directedoutwardly and whose gate is circled represents a p-type MOSFET.

In the specification, a MOSFET (Metal Oxide Semiconductor Field EffectTransistor) is abbreviated as a MOS. Note that the present invention canbe generally applied to a MISFET.

An entire charge pump circuit generating a plus high voltage accordingto a first embodiment of the present invention is shown in FIG. 5 and apartial extraction from charge pump stages is shown in FIG. 6. Thecharge pump circuit according to the present invention is one in whichbasic pump cells each including four n-type MOSs and two capacitancesare connected in series in a multistage manner. Each basic pump cell iscomposed of: a transfer MOS (TMOS) transferring electric charges to thenext stage; body controlled MOSs each serving as a connection circuitfor connecting a substrate (also referred to as well) of the TMOS to adrain or source of the transfer MOS; a gate voltage set MOS serving as aconnection circuit for connecting a gate potential of the transfer MOSto the drain; a charge capacitance (C) for charging the electric chargestransferred from the TMOS; and a transfer gate capacitance (Cg) fortransferring a potential of 2VCLK or 2VCLKn to the gate of the TMOS.Also, the gate of the TMOS is connected to a gate of the gate voltageset MOS at the next stage. However, the gate of the gate voltage set MOSat the first stage is connected to a connection point between the TMOSand the charge capacitance. All of these transfer MOS, body controlledMOSs, and gate voltage set MOS are implemented by using nMOSs.

Two-phase clock signals CLK and CLKn have operating voltages Vcc astheir amplitudes. Output timings of the clock signals CLK and CLKn aresuch that: the CLKn is at 0 V when the clock signal CLK is at theoperating voltage Vcc; the CLKn is at the operating voltage Vcc when theclock signal CLK is at 0 V; and these clock signals have anopposite-phase relation to each other.

Also, two-phase clock signals 2VCLK and 2VCLKn have 2Vcc, which is twiceas much as the operating voltage, as their amplitudes. Similarly to theCLK and CLKn, the 2VCLK and 2VCLKn are clock signals having anopposite-phase relation to each other.

The operations will be described below with reference to FIGS. 7 and 8.

In a period of CLK X1 shown in FIG. 7, since CLK=0 V and 2VCLKn=2Vcc, ann3 potential of a gate of the transfer MOS becomes equal to or higherthan 2Vcc and a T1 is turned ON, so that the electric charges aresupplied from the Vcc to a charge capacitance C1 and an n1 potentialeventually becomes the Vcc. Therefore, since the n1 potential is equalto or lower than the Vcc while the charge capacitance C1 is beingcharged, the gate of the nMOS is coupled to the n1 potential and t2 andt3, whose each source or drain is equal to or higher than the Vcc, areturned OFF. Also, since the gate of the nMOS is connected to the Vcc, at1 in which the n1 potential serving as a drain or source potential isequal to or lower than the Vcc is turned ON and a substrate potential n2of the T1, which is a transfer MOS, becomes the n1 potential, therebybeing coupled to the drain or source of the TMOS, whichever is lower inpotential. Here, the Vt0 of the transfer MOS is generally lower than theVcc and a n3, which is a gate potential of the transfer MOS, becomesequal to or higher than 2Vcc, so that the n1 potential increases to theVcc without a loss of the Vt0.

At a second stage, since CLKn=Vcc and 2VCLK=0 V, an n4 potential becomes(Q2/C2)+Vcc if it is assumed that the electric charges stored in acharge capacitance C2 are Q2. Here, if it is assumed that all of theelectric charges in the C1 have been transferred from the first stage,Vcc+(Q1/C1)=(Q2/C2)=2Vcc. Therefore, the n4 potential becomes the 3Vccand since n4 potential>n1 potential, a t5 in which the gate of the nMOSis coupled to the n4 potential is turned ON and the t4 in which the gateof the nMOS is coupled to the n1 potential is turned OFF. Since the t5is turned ON, a substrate potential n5 of a transfer nMOS T2 becomes then1 potential. Also, a t6 in which the gate of the nMOS is coupled to then3 potential is turned ON and an n6 potential that is a gate potentialof the T2 becomes the n5 potential, whereby the T2 is turned OFF.

An odd-numbered (2N−1)-th stage (N is equal to or larger than 1)including third and later stages is such that, similarly to the firststage, the TMOS is turned ON and a connection point between the chargecapacitance C(2N−1) and the TMOS is at Vcc×(2N−1). Also, aneven-numbered 2N-th stage is such that the TMOS is turned OFF and aconnection point between the charge capacitance C(2N) and the TMOS is atVcc+Vcc×2N.

In a period of CLK X2 shown in FIG. 8, since CLK=Vcc and 2VCLKn=0 V, then1 potential is charged by the charge capacitance C1 in the X1 periodand becomes an increased potential Vcc+Vcc=2Vcc. For this reason, the t2and t3, in which the gate of each nMOS is coupled to the n1 potential,are turned ON and the gate potential n3 of the transfer nMOS and thesubstrate potential n2 become the Vcc and the T1 is turned OFF.

At the second stage, since CLKn=0 V and 2VCLK=2Vcc and the n4 potentialis equal to or lower than the 2Vcc, the n1 potential≧the n4 potentialand the t4 in which the gate of the nMOS is coupled to the n1 potentialis turned ON and the t5 in which the n4 potential is coupled to the gateof the nMOS is turned OFF. For this reason, a substrate potential n5 ofthe transfer MOS T2 becomes the n4 potential. Also, when the t6 in whichthe n3 potential equal to the Vcc is coupled to the gate of the nMOS isturned OFF, the n6 potential becomes 3Vcc obtained by adding 2VCLK=2Vccto a potential having been made the Vcc in the X1 period and the T2 isturned ON. Due to this, the electric charges are moved from the chargecapacitances C1 to C2, and eventually the n4 potential becomes the 2Vcc.

The odd-numbered (2N−1)-th stage (N is equal to or larger than 1)including the third and later stages is such that, similarly to thefirst stage, the TMOS is turned OFF and the connection point between thecharge capacitance C(2N−1) and the TMOS becomes at a Vcc+Vcc×(2N−1).Also, the even-numbered 2N-th stage is such that the TMOS is turned ONand the connection point between the charge capacitance C(2N) and theTMOS becomes at a Vcc×2N.

FIG. 9 shows voltage states in the circuit in the CLK X1 and X2 periods.Here, a gate of a gate voltage set MOS of a TMOS at an N-th stage isconnected to a gate of a TMOS at an (N−1)-th stage, but the gate of thegate voltage set MOS of the TMOS at the first stage is coupled to andcontrols the n1 potential to which the charge pump capacitance C1 isconnected.

In this charge pump, if a voltage amplification factor per stage is aVga in the case of boosting the plus voltage, a voltage Vout outputtedfrom this charge pump can be represented by the following Equation (4).Vout=Vga×N+Vcc  (4)

-   -   N: number of stages and Vcc: power-supply voltage,        wherein the voltage amplification factor Vga becomes the maximum        Vcc. When a load current IL flows through the Vout,        ΔV=(IL×t)/C  (5)    -   C: charge pump capacitance and t: CLK cycle time.        Since a voltage drop of “ΔV” represented by Equation (5) occurs,        Vga=Vcc−ΔV  (6)        The Vga is represented as shown in Equation (6).

Here, when the load current IL flows, potentials at the respectiveconnection points shown in FIGS. 7 and 8 are such that: the connectionpoints shown in FIG. 7 have n1=n2=n5=n6=˜(Vcc−ΔV), n3=2Vcc, andn4=3Vcc−2ΔV; the connection points shown in FIG. 8 have n1=2Vcc−ΔV,n2=n3=Vcc, n4=n5=2Vcc−2ΔV, and n6=3Vcc−ΔV; and a voltage drop of (numberof stages×ΔV) occurs at the connection points n1 and n4 between thecharge capacitance and the TMOS at each stage.

FIG. 10 shows a simulated circuit of the body controlled charge pumpcircuit according to the present invention and FIG. 11 shows Spicesimulation results. In a circuit configuration where the number ofcharge pump stages is 13 and the charge pump capacitance is 70F/stage,on the conditions that load resistance (RLOAD)=100 MΩ and loadcapacitance (CLOAD)=100 pF, approximately 18.5 V is achieved when thepower-supply voltage Vcc=1.5 V and approximately 15.5 V is achieved whenthe power-supply voltage Vcc=1.3 V. Therefore, a high voltage equal toor higher than approximately 12 V required for deleting and writing thenon-volatile memory can be generated even at a low power-supply voltage.At the time of this Spice simulation, the Vt0 of the transfer MOS isapproximately 0.9 V and the substrate effect coefficient γ isapproximately 0.8.

Here, with reference to FIG. 12, an operation of a twice boosted CLKcircuit shown also in FIG. 10 will be described. The twice boosted CLKcircuit is a circuit for generating the 2VCLK and 2VCLKn from the CLKand CLKn as shown in FIGS. 5 to 8. Also in this twice boosted CLKcircuit, a charge pump scheme is used, and a pMOS is used as thetransfer MOS. When CLK=Vcc, a gate of a transfer pMOS become at 0 V andelectric charges are charged into the capacitance C. The n2 potentialbecomes the Vcc and, at the same time, the output thereof becomes 0 V.Next, when CLK=0 V, the n2 potential becomes 2×Vcc and the gate of thetransfer pMOS is set to the n2 potential, whereby the transfer pMOS isturned OFF. Also, an output thereof becomes 2×Vcc since the n2 potentialis outputted. Thus, the twice boosted CLK circuit generates a voltagewithin a range of 0 V to 2Vcc in synchronization with the inputted CLK.

Although FIGS. 5 to 12 relate to the charge pump generating a plus highvoltage, FIG. 13 shows a circuit for generating a minus high voltageaccording to a second embodiment of the present invention.

Although the circuit configuration is almost the same as that in FIG. 5,a phase of the CLK and a position of the gate voltage set MOS aredifferent. The drain and source of the gate voltage set MOS areconnected to an opposite side of the connection point between the TMOSand the charge capacitance C and to the gate of the TMOS in the case ofthe plus boosting shown in FIG. 5 while being connected to theconnection point between the TMOS and the charge capacitance C and tothe gate of the TMOS in the case of the minus boosting shown in FIG. 13.Also, in the case of the plus boosting shown in FIG. 5, the CLK and2VCLKn and the CLKn and 2VCLK become pairs, whereby each pump cell hasbeen controlled. However, in the case of the minus boosting shown inFIG. 13, the CLK and 2VCLK and the CLKn and 2VCLKn become pairs, wherebyeach pump cell is controlled. For this reason, in the case of the plusboosting, the plus high voltage is obtained by making the electriccharges flow in a charge capacitance at the next stage. However, adirection of flow of the electric charges in the case of the minus oneis made reverse to that in the case of the plus, so that the electriccharges are made to flow in the preceding stage, whereby the minus highvoltage is obtained.

Furthermore, the gate of the gate voltage set MOS of a TMOS at an N-thstage is connected to a gate of a TMOS at an (N−1)-th stage, and thegate of the gate voltage set MOS of the TMOS at the first stage iscoupled to and controls the CLKn. The substrate of the gate voltage setMOS of the TMOS at each stage is coupled to the substrate potential ofthe transfer MOS at each stage.

An operation thereof will be described by using FIGS. 14 and 15. In aperiod of CLK X1 shown in FIG. 14, CLK=0 V and 2VCLK=0 V, and the n3potential of the gate of the transfer MOS at the first stage is suchthat since the gate of the gate voltage set MOS is coupled to CLKn=Vcc,the gate voltage set MOS is turned ON and the n3 potential and the n1potential are coupled to each other. During the operation, the n1potential is within a range of −Vcc to 0 V, so that the T1 is turnedOFF. Also, the substrate potential n2 of the T1 is such that the t2 isturned OFF and the t1 is turned ON and the n2 potential and the n1potential are coupled to each other.

At the second stage, CLKn=Vcc and 2VCLKn=2Vcc, and an n6 potential ofthe gate of the T2 is within a range of approximately −2Vcc toapproximately 0 V due to the 2VCLK. Also, the n3, which is a gatepotential of the t6, is such that since the t6 is turned OFF atapproximately −Vcc, the T2 is turned ON and the n4 potential becomes−Vcc equal to the n1 potential. Also, the n5 potential is such thatsince the n4 potential is higher than the n1 potential by approximatelyVcc immediately after the CLK becomes the Vcc, the t5 is turned ON andthe n5 potential becomes identical to the n1 potential.

In a period X2 shown in FIG. 15, CLK=Vcc and 2VCLK =2Vcc and the n3potential is changed from −Vcc to Vcc due to the 2VCLK. Also, the t3 isturned OFF due to CLKn=0 V, so that the T1 is turned ON and the n1potential becomes 0 V. Furthermore, the n2 potential is such that sincethe n1 potential is higher than the n1 potential by approximately Vccimmediately after the CLK becomes the Vcc, the t2 is turned ON and then2 potential becomes 0 V.

At the second stage, CLKn=0 V and 2VCLKn=0 V, and the n6 potential ofthe gate of the T2 becomes within a range of approximately 0 V toapproximately −2Vcc due to the 2VCLK. Also, the n4 potential is changedfrom −Vcc to −2Vcc due to the CLKn and “the gate potential n3 oft6”=Vcc, so that the t6 is turned ON and the n6 potential and the n4potential are coupled to each other and the T2 is turned OFF. Further,since the t4 is turned ON, the n5 potential becomes −2Vcc equal to then4 potential.

Here, in the case of the minus voltage boosting, if a voltageamplification factor per stage is Vga, the voltage Vout outputted fromthis charge pump can be represented by the following Equation (7):Vout=Vga×N  (7)

-   -   N: number of stages and Vcc: power-supply voltage.        The voltage amplification factor Vga becomes the Vcc at maximum.

FIGS. 5 to 15 relate to the charge pump circuit in which the transferMOS, the body controlled MOSs, and the gate voltage set MOS areconfigured by the nMOSs. However, a third embodiment, which isconfigured by pMOSs and is a charge pump circuit according to thepresent invention, is shown in FIG. 16 and a fourth embodiment thereofis shown in FIG. 17.

FIG. 16 is a plus boosting change pump circuit in which pMOSs are usedfor the TMOS, body controlled MOSs, and gate voltage set MOS. Also, theCLK and 2VCLK and the CLKn and 2VCLKn, which have the same clocks inphase, become pairs and control each pump cell, so that the electriccharges are transferred from the pump cell at the previous stage to therelevant pump cell and the plus boosting is further executed inaccordance with progress to the subsequent stages. Also, unlike the caseof the nMOS, the substrate of the transfer MOS is set by the bodycontrolled MOS to the drain or source potential of the transfer,whichever is higher in potential.

FIG. 17 is a minus boosting charge pump circuit. Unlike the case of theplus boosting shown in FIG. 16, the gate voltage set MOS is disposed ona side opposite to the charge capacitance, and the CLK and 2VCLKn andthe CLKn and 2VCLK, which have clocks reversed in phase, become pairsand control each pump cell. For this reason, the electric charges aretransferred from the relevant pump cell to the pump cell at thepreceding stage, and the minus boosting is further executed inaccordance with progress to the subsequent stages. Also, similarly tothe plus boosting shown in FIG. 16, the substrate of the transfer MOS isset by the body controlled MOS to the drain or source potential of thetransfer, whichever is higher in potential. As seen also from FIGS. 16and 17, the circuit configuration is identical to that in the case ofuse of the nMOSs. The plus booster circuit using the pMOSs shown in FIG.16 has the same circuit configuration as that of the minus boostercircuit using the nMOSs shown in FIGS. 14 and 15, and the minus boostercircuit using the pMOSs shown in FIG. 17 has the same circuitconfiguration as that of the plus booster circuit using the nMOSs shownin FIGS. 5 to 8, so that even if either of the pMOS and nMOS is used,the plus and minus boosted voltages can be obtained by the same circuitconfiguration.

In controlling the non-volatile memory, for example in some cases, aminus high voltage may be required at deletion and a plus high voltagemay be required at writing. In this case, separate manufacture of plusand minus charge pump circuits causes an increase in chip areas, wherebychip prices rise. Therefore, based on the fact that deletion and writingdo not occur simultaneously, a charge pump circuit, which generates aplus or minus high voltage by using a single one and is a fifthembodiment of the present invention, is suggested by FIG. 18. Althoughthe basic circuits thereof are the same as that in FIG. 5 and the basicoperation thereof is also the same as that described with reference toFIGS. 7 and 8, this embodiment has a feature in which the input andoutput can be reversed by a selection circuit and a selection signal ata time of occurrence of a plus high voltage or at a time of occurrenceof a minus high voltage. The operation at the occurrence of the plushigh voltage is the same as that described with reference to FIGS. 5 to8, wherein the input is set to a Vdd on the left side in FIG. 18 and theoutput is set on the right side in FIG. 18. At the occurrence of theminus high voltage, the input is set to 0 V on the right side in FIG. 18and the output is set on the left side in FIG. 18. The movement of theelectric charges at the occurrence of the plus and minus high voltagesis changed from left to right in FIG. 18. Therefore, in the case of theminus one, the electric charges flow into 0 V and accordingly theprevious stage becomes gradually negatively charged, whereby the minushigh voltage can be generated.

Next, in controlling the non-volatile memory, for example in some cases,two types of high voltages, such as 12 V and 6 V, may be simultaneouslyrequired. A sixth embodiment according to the present invention, whichis a circuit configuration for generating a first high voltage outputtedfrom the charge pump circuit shown in FIG. 5 and generating a secondhigh voltage by using this first high voltage, is shown in FIG. 19. Abody controlled parallel-type charge pump shown in FIG. 19 is identicalto that shown in FIG. 5. A serial-type charge pump of FIG. 19, which isa seventh embodiment of the present invention, is shown in FIG. 20. Theserial-type charge pump has a feature in which: a potential twice asmuch as the first high voltage can be obtained by using the transferpMOS and turning ON or OFF the charge capacitance at the first highvoltage; and an internal series block 1 and an internal series block 2are alternately turned ON and OFF by using a CLK signal of theserial-type charge pump.

FIG. 21 shows a hardware configuration of an IC card on which thebooster circuit according to the present invention is mounted. Thebooster circuit according to the present invention is mounted on a flashmemory and a EEPROM in IC card hardware.

Also, since the flash memory and the EEPROM require plus or minus highvoltages at the time of writing or deleting data, the booster circuitaccording to the present invention is used. However, the booster circuitaccording to the present invention can be used at the reading to checkwhether a memory subjected to writing and deletion reaches an expectedthreshold.

In the following, the charge pump circuit described in the aboveembodiments can be applied to, for example, an LSI circuit, an IC cardchip, and an IC card including a non-volatile memory typified by anEEPROM and a flash memory, which requires a plus or minus high voltageother than a power-supply voltage.

INDUSTRIAL APPLICABILITY

The present invention is used in a non-volatile memory, an IC chiprequiring a voltage equal to or higher than a power-supply voltage, orthe like.

1. A booster circuit connecting and boosting basic charge pump cellsdisposed respectively at N stages, the booster circuit comprising: saidbasic charge pump cells each including at least a first MISFET, a secondMISFET, a third MISFET, and a first capacitor, a fourth MISFET, and asecond capacitor, wherein a back gate of said first MISFET is connectedto a first node, and a source-drain path thereof is connected between asecond node and a third node, a back gate of said second MISFET isconnected to said first node, and a source-drain path thereof isconnected between said first node and said second node, a back gate ofsaid third MISFET is connected to said first node, and a source-drainpath thereof is connected between said first node and said third node,one end of said first capacitor is connected to said third node, and afirst clock with an amplitude of an operating voltage is inputted to theother end thereof, said third node is connected to a second node of saidbasic charge pump cell at a next stage, one end of said second capacitoris connected to a gate of said first MISFET, and a second clock, havinga voltage amplitude larger than that of a sum of said operating voltageand a threshold voltage of said first MISFET and being a reversed phaseto said first clock, is inputted to the other end thereof, and a backgate of said fourth MISFET is connected to said first node, asource-drain path thereof is connected between said second node and thegate of said first MISFET, and, for each of the N stages other than afirst stage, a gate thereof is connected said one end of said secondcapacitor configuring said basic charge pump cell at a preceding stage.2. The booster circuit according to claim 1, wherein said first, second,third, fourth MISFETs are n-type MISFETs, and a voltage is boosted on apositive side.
 3. The booster circuit according to claim 1, wherein saidfirst, second, third, and fourth MISFETs are p-type MISFETs, and avoltage is boosted on a negative side.
 4. The booster circuit accordingto claim 1, further comprising: a twice boosted clock generating circuitfor generating a clock of a voltage twice as much as said operatingvoltage, and wherein said twice boosted clock generating circuitgenerates said second clock.
 5. The booster circuit according to claim1, further comprising: a selection circuit for choosing which of plus orminus voltages is boosted.
 6. The booster circuit according to claim 5,Wherein said selection circuit is a circuit for connecting a second nodeof one of said basic charge pump cell at a first stage and said basiccharge pump cell at a last stage to said operating voltage, and forconnecting a third node of the other thereof to a ground potential. 7.The booster circuit according to claim 1, further comprising: aserial-type charge pump, wherein said serial-type charge pump outputs asecond voltage from a first voltage outputted from said booster circuit.8. A non-volatile memory executing at least one of reading, writing, anddeletion in accordance with a voltage generated by the booster circuitaccording to claim
 1. 9. An IC card having the non-volatile memoryaccording to claim
 8. 10. A booster circuit connecting and boostingbasic charge pump cells disposed respectively at N stages, the boostercircuit comprising: said basic charge pump cells each including at leasta first MISFET, a second MISFET, a third MISFET, a first capacitor, afourth MISFET, and a second capacitor, wherein a back gate of said firstMISFET is connected to a first node, and a source-drain path thereof isconnected between a second node and a third node, a back gate of saidsecond MISFET is connected to said first node, and a source-drain paththereof is connected between said first node and said second node, aback gate of said third MISFET is connected to said first node, and asource-drain path thereof is connected between said first node and saidthird node, one end of said first capacitor is connected to said thirdnode, and a first clock with an amplitude of an operating voltage isinputted to the other end thereof, said third node is connected to asecond node of said basic charge pump cell at a next stage, one end ofsaid second capacitor is connected to a gate of said first MISFET, and asecond clock, having a voltage amplitude larger than that of a sum ofsaid operating voltage and a threshold voltage of said first MISFET andhaving a same phase as said first clock, is inputted to the other endthereof, and a source-drain path of said fourth MISFET is connectedbetween said third node and the gate of said first MISFET, and, for eachof the N stages other than a first stage, a gate thereof is connectedsaid one end of said second capacitor configuring said basic charge pumpcell at a preceding stage.
 11. The booster circuit according to claim10, wherein said first, second, third, and fourth MISFETs are n-typeMISFETs, and a voltage is boosted on a negative side.
 12. The boostercircuit according to claim 10, wherein said first, second, third, andfourth MISFETs are p-type MISFETs, and a voltage is boosted on apositive side.
 13. The booster circuit according to claim 10, whereinsaid first clock inputted to said basic charge pump cells atodd-numbered stages and said first clock inputted to said basic chargepump cells at even-numbered stages are opposite in phase, and saidsecond clock inputted to said basic charge pump cells at theodd-numbered stages and said second clock inputted to said basic chargepump cells at the even-numbered stages are opposite in phase.
 14. Abooster circuit connecting and boosting basic charge pump cells disposedrespectively at N stages, the booster circuit comprising: said basiccharge pump cells each including: an n-type transfer MISFET, and a firstconnection circuit for connecting a drain or source of said transferMISFET, whichever is lower in potential, and a back gate of saidtransfer MISFET; a circuit applying, to a gate of said transfer MISFETvia a capacitance, a voltage having a voltage amplitude larger than thatof a sum of an operating voltage and a threshold voltage of saidtransfer MISFET; and a second connection circuit for connecting the gateof said transfer MISFET and one of the drain and source thereof whensaid transfer MISFET is in an OFF state.
 15. The booster circuitaccording to claim 14, wherein said first connection circuit isconfigured by a first body controlled MISFET and a second bodycontrolled MISFET, and one of said first and second body controlledMISFETs is conducted, and the drain or source of said transfer MISFET,whichever is lower in potential, and the back gate of said transferMISFET are connected.
 16. The booster circuit according to claim 14,wherein said second connection circuit is a gate voltage set MISFET,whose drain-source path is connected between the gate and the drain orsource of said transfer MISFET, and, for each of the N stages other thana first stage, in which a gate voltage of said transfer MISFET in thepump cell at a preceding stage is applied to a gate value thereof.
 17. Abooster circuit connecting and boosting basic charge pump cells disposedrespectively at N stages, the booster circuit comprising: said basiccharge pump cells each including: a p-type transfer MISFET; a firstconnection circuit for connecting a drain or source of said transferMISFET, whichever is lower in potential, and a back gate of saidtransfer MISFET; a circuit applying, to a gate of said transfer MISFETvia a capacitance, a voltage having a voltage amplitude larger than thatof a sum of an operating voltage and a threshold voltage of saidtransfer MISFET; and a second connection circuit for connecting the gateof said transfer MISFET to one of the drain and source thereof when saidtransfer MISFET is in an OFF state.
 18. The booster circuit according toclaim 17, wherein said first connection circuit is configured by a firstbody controlled MISFET and a second body controlled MISFET, and one ofsaid first and second body controlled MISFETs is conducted, and thedrain or source of said transfer MISFET, whichever is lower inpotential, and the back gate of said transfer MISFET are connected. 19.The booster circuit according to claim 17, wherein said secondconnection circuit is a gate voltage set MISFET, whose drain-source pathis connected between the gate and the drain or source of said transferMISFET, and, for each of the N stages other than a first stage, in whicha gate voltage of said transfer MISFET in the pump cell at a precedingstage is applied to a gate value thereof.